Since the invention of the integrated circuit (IC), semiconductor chip features have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC's with hundreds of millions of transistors at feature sizes of 0.25 micron, 0.18 micron, and less are becoming routine. Improvement in overlay tolerances in photolithography, and the introduction of new light sources with progressively shorter wavelengths, have allowed optical steppers to significantly reduce the resolution limit for semiconductor fabrication far beyond one micron. To continue to make chip features smaller, and increase the transistor density of semiconductor devices, IC's have begun to be manufactured that have features smaller than the lithographic wavelength.
One feature that has particularly decreased in size is the transistor gate. A gate is the control electrode in a field-effect transistor (FET). A voltage applied to the gate regulates the conducting properties of the semiconductor channel region, which is usually located directly beneath the gate. In a MESFET (metal semiconductor field effect transistor), the gate is in intimate contact with the semiconductor. In a MOSFET (metal oxide semiconductor field effect transistor), it is separated from the semiconductor by a thin oxide, typically 100–1000 angstroms thick.
Most current semiconductor fabrication processes can achieve gates that have a width no smaller than 0.05 micron. These processes may use photoresist dry trimming to achieve so-called narrow gates of this width. Photoresist trimming is the process by which photoresist that has been applied to a semiconductor substrate is exposed to an exposure light source according to a pattern, developed to remove the part of the photoresist that was exposed, and finally further trimmed to remove even more of the photoresist. The part of the photoresist that was not exposed because it was beneath under opaque regions of the pattern during exposure usually remains. The polysilicon or other material deposited on the substrate below the photoresist is then trimmed to form gates and other features within the polysilicon.
Patterning and trimming can be dry etching or wet etching processes. Wet etching refers to the use of wet chemical processing to selectively remove the material from the wafer. The chemicals are placed on the surface of the wafer, or the wafer itself is submerged in the chemicals. Dry etching refers to the use of plasma stripping, using a gas such as oxygen (O2), C2F6 and O2, or another gas. Whereas wet etching is a low-temperature process, dry etching is typically a high-temperature process.
U.S. Pat. No. 6,174,818 describes one approach to photoresist trimming to achieve narrow gate electrodes. As shown in FIG. 1A, on top of a silicon wafer substrate 102 is deposited, in order, a stop layer 104, a polysilicon layer 106 from which ultimately a gate will be formed, a hard mask layer 108, and a (soft) photoresist layer 110. The stop layer 104 is typically a type of oxide, and prevents etchant from removing material beyond the stop layer 104. The hard mask layer 108 may be silicon dioxide, silicon nitride, an inorganic anti-reflecting coating (ARC), or another type of hard mask.
The photoresist layer 110 is exposed to a light source through a pattern, and then etched by a development process to remove those parts of the layer 110 that were exposed to the light source, so that only those parts of the layer 110 that were not exposed to the light source remain. The resulting photoresist layer 110 is then further trimmed to remove more of the layer 110. This is shown in FIG. 1B. The photoresist layer 110 has a smaller width in FIG. 1B as compared to in FIG. 1A, and also has some decrease in its height. The smaller width results from the parts of the layer 110 that were exposed to the light source being completely removed via development, and then trimming some of the remaining photoresist layer 110 to achieve a still narrower part of the layer 110 that remains. Trimming removes some of the height of the photoresist layer 110, which is why the layer 110 has a smaller height in FIG. 1B than in FIG. 1A.
The hard mask layer 108 is next etched to remove the exposed parts of the hard mask layer 108 that are not beneath the remaining photoresist layer 110. This is shown in FIG. 1C. The hard mask layer 108 has a width substantially equal to that of the photoresist layer 110. The etching that removes the exposed parts of the hard mask layer 108 also removes some more of the remaining photoresist layer 110. The layer 110 in FIG. 1C therefore has a smaller height than it does in FIG. 1B. The remaining photoresist layer 110 is then removed, as shown in FIG. 1D, such as by a photoresist stripping process.
The polysilicon layer 106 is next etched via a gate etching process to remove the exposed parts of the layer 106 that are not beneath the remaining hard mask layer 108. This is shown in FIG. 1E. The etching forms the gate within the polysilicon layer 106, so that the layer 106 has a width corresponding to the width of the hard mask layer 108 that remains. The stop layer 104 is also etched to substantially the silicon substrate 102. The stop layer 104 acts to stop the etching process from etching the substrate 102 itself, where etching of the thin layer 104 is slower than the thicker layer 106. Finally, the hard mask layer 108 is removed, as shown in FIG. 1F, resulting in the finished gate as the remaining polysilicon layer 106, on top of the stop layer 104 and the substrate 102.
The photoresist trimming that results in FIG. 1B is referred to as critical dimension (CD) trimming. This is because it is the process that defines the CD of the semiconductor device being fabricated, the gate in the remaining polysilicon layer 106 in FIG. 1F. That is, the width of the polysilicon layer 106 in FIG. 1F is substantially identical to the width of the hard mask layer 108 in FIG. 1E, which itself is substantially identical to the width of the photoresist layer 110 in FIG. 1B. Controlling the width of the photoresist layer 110 during photoresist trimming from FIG. 1A to FIG. 1B thus ultimately controls the width of the gate in the polysilicon layer 106 in FIG. 1F. The gate width is a CD of the semiconductor device being fabricated, where a CD is generally defined as a geometry or space used as a gauge to monitor the pattern size and ensure that it is within a customer's specification.
However, photoresist trimming can only trim about 0.05 micron from the width of a photoresist layer, limiting how narrow the width of a gate can be fabricated. Where the width of the photoresist layer is initially 0.11 micron, for instance, this means that the narrowest the CD width of a gate that can be fabricated is 0.06 micron. This is problematic, because new semiconductor device designs may require a gate with a much smaller width. For example, some new semiconductor device designs may require a gate having a width of 0.035 micron. Furthermore, even achieving photoresist trimming of about 0.05 micron is difficult, because local pattern density and other effects may cause defects in the semiconductor devices resulting from such large-scale trimming.
Local pattern density effects are those that result from some semiconductor features being less or more dense in a desired pattern than other features. For example, in an etch process that forms metal lines by etching all but narrow strips of a blanket metal layer, isolated lines of a given designed width may end up wider on the wafer than densely-packed lines of the same designed width due to etch-loading. This results in variation of similarly designed features on the resulting semiconductor device depending on the density of those features in the desired pattern. Other pattern density effects include metal, such as copper and aluminum, recession, dielectric erosion, feature edge rounding, and large-scale feature non-uniformities.
The limit to which photoresist trimming can be achieved is thus substantially 0.05 micron, assuming that local pattern density and other effects can be otherwise controlled. This is shown in the graph 200 of FIG. 2. The x-axis 202 measures trimming time in seconds, whereas the y-axis 204 measures CD bias, which corresponds to in absolute terms the amount of photoresist width that can be trimmed, in nanometers (nm). As indicated by the line 206, acceptable photoresist trimming can be accomplished for a duration between 40 seconds, as denoted by the point 208, and 100 seconds, as denoted by the point 210. At 40 seconds, at the point 208, photoresist trimming results in a CD bias of little less than −20 nm, which corresponds to 0.02 micron of the photoresist width being trimmed. The CD bias increases in absolute terms until it reaches 100 seconds, at the point 210, at which photoresist trimming results in a CD bias of nearly −50 nm. This corresponds to 0.05 micron of the photoresist width being trimmed.
U.S. Pat. No. 6,013,570 describes a solution to avoid the local pattern density effects that can result from the wide-scale photoresist trimming of U.S. Pat. No. 6,174,818 that has been described with reference to FIGS. 1A–1F. First, as shown in FIG. 3A, on top of a silicon wafer substrate 302 is deposited, in order, a stop layer 304, a polysilicon layer 306 from which ultimately a gate will be formed, a hard mask layer 308, and a (soft) photoresist layer 310. The stop layer 304 is typically a type of oxide, and prevents etchant from removing material beyond the stop layer 304. The hard mask layer 308 may be silicon dioxide, silicon nitride, an inorganic ARC, or another type of hard mask.
The photoresist layer 310 is exposed to a light source through a pattern, and then developed to remove those parts of the layer 310 that were exposed to the light source, so that only those parts of the layer 310 that were not exposed to the light source remain. This is shown in FIG. 3B. The photoresist layer 310 has a smaller width in FIG. 3B as compared to in FIG. 3A. The smaller width results from the parts of the layer 310 that were exposed to the light source being completely removed.
The hard mask layer 308 is next etched to remove the exposed parts of the hard mask layer 308 that are not beneath the remaining photoresist layer 310. This is shown in FIG. 3C. The hard mask layer 308 has a width substantially equal to that of the photoresist layer 310. The etching that removes the exposed parts of the hard mask layer 308 also removes some of the remaining photoresist layer 310. The layer 310 in FIG. 3C therefore has a smaller height than it does in FIG. 3B.
The polysilicon layer 306 is next etched via a gate etching process to remove the exposed parts of the layer 306 that are not beneath the remaining polysilicon layer 310 and the remaining hard mask layer 308. This is shown in FIG. 3D. The etching forms the gate within the polysilicon layer 306, so that the layer 306 has a width corresponding to the width of the hard mask layer 308 that remains. The stop layer 304 acts to stop the etching process from etching the substrate 302 itself. The etching that removes the exposed parts of the polysilicon layer 306 also removes some more of the remaining photoresist layer 310, which is why the layer 306 has a smaller height in FIG. 3D than in FIG. 3C.
The remaining photoresist 306 is then removed, such as by using a photoresist stripping process, and the width of the polysilicon layer 306 is further decreased by isotropic etching. This is shown in FIG. 3E. The isotropic etching does not affect the width of the stop layer 304, however, such that the stop layer 304 serves to prevent the isotropic etching from etching the substrate 302. Finally, the hard mask layer 308 is removed, as shown in FIG. 3F, resulting in the finished gate as the remaining polysilicon layer 306, on top of the stop layer 304 and the substrate 302. The removal of the hard mask layer 308 may also remove the parts of the stop layer 304 that are not directly beneath the layer 306, such that the stop layer 304 again serves to protect the substrate 302 from being removed.
The width of the resulting gate formed in the polysilicon layer 306 in FIG. 3F is substantially the same as that of the resulting gate formed in the polysilicon layer 106 in FIG. 1F. The photoresist patterning resulting in FIG. 3B results in less width of the photoresist layer 310 being removed than the width of the photoresist layer 110 in FIG. 1B resulting from photoresist trimming. To achieve the same resulting gate width, the approach that has been immediately described performs its CD process by the isotropic etching of the polysilicon layer 306 that results in FIG. 3E. The isotropic etching resulting in FIG. 3E is thus referred to as CD etching, because it is the process that defines the CD of the semiconductor device being fabricated, the gate in the remaining polysilicon layer 306 in FIG. 3F.
The approach of U.S. Pat. No. 6,013,570 described with reference to FIGS. 3A–3F avoids the local pattern density effects that can result from large-scale photoresist removal, such as that which the approach of U.S. Pat. No. 6,174,818 described with reference to FIGS. 1A–1F accomplishes. This is because the former approach avoids having to remove as much photoresist by the patterning that results in FIG. 3B as the latter approach does by the patterning and trimming that results in FIG. 1B. However, the approach of U.S. Pat. No. 6,013,570 is still disadvantageous, owing to its reliance on isotropic etching the polysilicon layer 306 as the CD process that results in FIG. 3E.
Isotropic etching, in the context of FIG. 3E, is the removal by etchant of the polysilicon layer 306 even beneath the hard mask layer 308. Isotropic etching is controlled only with difficulty. Over etching may result, which is more isotropic etching than desired. Furthermore, too much isotropic etching can result in lifting of the hard mask layer 308, such that the polysilicon layer 306 is significantly etched even directly beneath the hard mask layer 308, as a result of the layer 308 peeling upward. Isotropic etching uses a non-selective etchant, which in high-density devices having multiple layer stacks can result in microloading. Microloading is a change in the local etch rate relative to the area of material being removed, which also causes the isotropic etching resulting in FIG. 3E to be difficult to control. To this end, using isotropic etching to avoid the local pattern density effects of large-scale photoresist trimming effectively replaces one set of problems and difficulties with another.
In any case, neither the approach of U.S. Pat. No. 6,174,818, nor the approach of U.S. Pat. No. 6,013,570, can achieve a gate width of substantially less than 0.06 micron when beginning with a photoresist layer having an initial width of 0.11 micron. Whereas the former approach may experience local pattern density effects, the latter approach may experience isotropic etching difficulties. Neither approach, however, typically provides for the fabrication of ultra-narrow transistor gates, generally defined as gates resulting from (soft) photoresist and/or hard mask trimming in excess of 0.05 micron. For example, starting with photoresist and hard layers having an initial width of 0.11 micron, such ultra-narrow gates may have a width less than 0.06 micron, and perhaps as narrow 0.035 micron. For this and other reasons, therefore, there is a need for the present invention.